This invention relates to a current comparator having first and second inputs for receiving first and second input currents, first and second current memory circuits for sensing and storing the received currents during a first phase of a clock period and reproducing said received currents during a second non-overlapping phase of said clock period, first and second cross coupled transistors forming a latching circuit, means for feeding the stored and an inverted version of the received currents to the latching circuit during said second phase and means for feeding an output of the latch circuit to an output of the comparator circuit during the third phase of the clock period.
Such a current comparator has been disclosed in EP-A-0 744 032, in related U.S. Pat. No. 5,714,894 and in a paper entitled "A Full Nyquist 15 MS/s 8-b Differential Switched-Current A/D Converter" by Mark Bracy, William Redman-White, Judith Richardson and John B Hughes published in IEEE Journal of Solid-State Circuits, Vol 31, No 7, July 1996 at pages 945 to 951. The folded structure of the input and latching circuits used has a number of penalties. First the bias current drain is 4 J plus the current in the local reference generator, that is the input stage has doubled the required bias current. Secondly, the input stage has a similar number of transistors to the latch so the complexity is nearly doubled. Thirdly, the input stage generates the same noise as the latch and so there is a 3 dB noise penalty.